Conventionally, in printer head drivers or the like, shift registers are provided that receive data on a bit-by-bit basis as serial data and store it therein. In this shift register, the inputted serial data is divided on a bit-by-bit basis, then converted into parallel data, and then fed to a latch circuit. Each bit of data, having been stored in the latch circuit, is then outputted from the latch circuit to a drive circuit with predetermined timing determined on a bit-by-bit-basis, permitting electric current to be fed to a heating resistance or a light-emitting element.
As a printing apparatus provided with such a conventional printer head driver, there has been proposed a printing apparatus in which a plurality of heating elements are divided into a plurality of blocks, and a plurality of shift registers of the same number of bits as the number of heating elements of each block are provided (see Patent Publication 1). In this printing apparatus, data of each block is stored in each shift register, and the individual shift registers are driven with different timing. This makes it possible to separate a shift register performing data output and a shift register performing data input, making it possible to speed up printing operation.
As described above, when a shift register is provided on a block-by-block basis, a plurality of shift registers are built in a semiconductor integrated circuit device. Specifically, as shown in FIG. 8, a 64-bit shift register SRX composed of flip-flops FF1 to FF64 and a 64-bit shift register SRY composed of flip-flops FF65 to FF128 are built in a single semiconductor integrated circuit device 100. Now, the semiconductor integrated circuit device 100 has an input terminal SI1 that receives serial data to the shift register SRX, a clock input terminal CLK that receives a clock, an output terminal SO1 that outputs serial data from the shift register SRX, and an input terminal SI2 that receives serial data to the shift register SRY. Moreover, the flip-flop FF1 of the shift register SRX and the flip-flip FF65 of the shift register SRY each have, on the input side thereof, an input driver Din, and the flip-flop FF64 of the shift register SRX has, on the output side thereof, an output driver Dout.
Patent Publication 1: Japanese Patent Application Laid-Open No. H5-229159